Image sensor and image capturing device

ABSTRACT

An image sensor includes: a photoelectric conversion unit that photoelectrically converts incident light and generates a charge; and an A/D conversion unit that converts the analog signal generated due to charge generated by the photoelectric conversion unit into a digital signal, wherein: the A/D conversion unit includes a comparison unit that compares the analog signal with a reference signal and a first circuit layer including a first capacitor for generating the reference signal and a second circuit layer laminated to the first circuit layer and including with a second capacitor for generating the reference signal.

This is a Continuation of application Ser. No. 16/302,432 filed Nov. 16, 2018, which is a National Stage Application of PCT/JP2017/007551 filed Feb. 27, 2017, which in turn claims priority to Japanese Application No. 2016-101276 filed May 20, 2016. The entire disclosures of the prior applications are hereby incorporated by reference herein in their entireties.

TECHNICAL FIELD

The present invention relates to an image sensor and to an image capturing device.

BACKGROUND ART

An image sensor is known (refer to Patent Document #1) that comprises a first semiconductor chip including a photodiode, a second semiconductor chip including an analog/digital conversion unit, and a third semiconductor chip including a memory element, all laminated together. However, it is known that, when a plurality of elements are disposed, the chip area of the image sensor increases.

CITATION LIST Patent Literature

Patent Document #1: Japanese Laid-Open Patent Publication 2014-195112.

SUMMARY OF INVENTION

According to the 1st aspect of the present invention, an image sensor comprises: a photoelectric conversion unit that photoelectrically converts incident light and generates a charge; and an A/D conversion unit that converts the analog signal generated due to charge generated by the photoelectric conversion unit into a digital signal, wherein: the A/D conversion unit includes a comparison unit that compares the analog signal with a reference signal and a first circuit layer including a first capacitor for generating the reference signal and a second circuit layer laminated to the first circuit layer and including with a second capacitor for generating the reference signal.

According to the 2nd aspect of the present invention, an image capturing device comprises: an image sensor according to the 1st aspect; and an image generation unit that generates image data on the basis of a signal from the image sensor.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing the structure of an image capturing device according to a first embodiment;

FIG. 2 is a figure showing the cross sectional structure of an image sensor according to the first embodiment;

FIG. 3 is a circuit diagram showing the structure of a pixel according to the first embodiment;

FIG. 4 is a circuit diagram showing the structure of an A/D conversion unit and a signal generation unit according to the first embodiment;

FIG. 5 is a figure for explanation of an example of operation of an A/D conversion unit according to the first embodiment;

FIG. 6 is a circuit diagram showing the structure of an A/D conversion unit and a signal generation unit according to a second embodiment;

FIG. 7 is a circuit diagram showing the structure of a PGA unit according to a third embodiment; and

FIG. 8 is a circuit diagram showing the structure of an A/D conversion unit and a signal generation unit according to a first variant embodiment.

DESCRIPTION OF EMBODIMENTS First Embodiment

FIG. 1 is a block diagram showing the structure of an image capturing device according to a first embodiment. The image capturing device 1 includes a photographic optical system 2, an image sensor 3, and a control unit 4. The image capturing device 1 may, for example, be a camera. The photographic optical system (i.e. the image focusing optical system) 2 forms a subject image on the image sensor 3. The image sensor 3 captures the subject image formed via the photographic optical system 2 and generates an image signal. The image sensor 3 may, for example, be a CMOS image sensor. The control unit 4 outputs a control signal to the image sensor 3 for controlling the operation of the image sensor 3. Moreover, the control unit 4 performs image processing of various types upon the image signal outputted from the image sensor 3, and thus functions as an image generation unit that generates image data. It should be understood that it would be acceptable to arrange for the photographic optical system to be detachable from the image capturing device 1.

FIG. 2 is a figure showing the cross sectional structure of the image sensor according to the first embodiment. The image sensor 3 shown in FIG. 2 is a backside-illumination image sensor. The image sensor 3 includes a first substrate 111, a second substrate 112, a third substrate 113, and a fourth substrate 114. Each of the first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 is constituted as a semiconductor substrate. The first substrate 111 is laminated to the second substrate 112, the second substrate 112 is laminated to the third substrate 113, and the third substrate 113 is laminated to the fourth substrate 114. The second substrate 112 and the third substrate 113 include a plurality of through electrodes such as through silicon vias or the like. Circuitry provided upon each of the first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 is electrically interconnected by connection portions 109 and the through electrodes 110. The connection portions 109 may, for example, be bumps or electrodes or the like, and the through electrodes 110 may, for example, be through silicon vias.

Incident light L shown by the outlined white arrow sign is incident along the +Z axis direction. Moreover, as shown on the coordinate axes, the rightward direction upon the drawing paper which is orthogonal to the Z axis is taken as being the +X axis direction, and the direction orthogonal to the Z axis and also orthogonal to the X axis and outward from the drawing paper toward the viewer is taken as being the +Y axis direction. In the direction of incidence of the incident light L, the first substrate 111, the second substrate 112, the third substrate 113, and the fourth substrate 114 are laminated together in that order in the image sensor 3. The first substrate 111 is built to include a plurality of pixels 10 that are disposed in a two dimensional array. The plurality of pixels 10 are disposed along the X axis direction and along the Y axis direction. An example of the structure of the pixels 10 will be described hereinafter in detail with reference to FIG. 3.

The image sensor 3 further includes a micro-lens layer 101, a color filter layer 102, and a passivation layer 103. These layers, i.e. the passivation layer 103, the color filter layer 102, and the micro-lens layer 101, are laminated upon the first substrate 111 in that order. The micro-lens layer 101 includes a plurality of micro-lenses ML. Each of these micro-lenses ML condenses incident light onto a photoelectric conversion unit 12 that will be described hereinafter. The color filter layer 102 includes a plurality of color filters F. The passivation layer 103 is made from a nitride film and an oxide film.

FIG. 3 is a circuit diagram showing the structure of a pixel of the image sensor according to the first embodiment. The pixel 10 includes a photoelectric conversion unit 12 such as a photodiode (PD) or the like and a readout section 20. The photoelectric conversion unit 12 has the function of converting incident light into charge, and accumulating the charge that has been thus photoelectrically converted. And the readout section 20 includes a transfer unit 13, a discharge unit 14, a floating diffusion (FD) 15, an amplification unit 16, and a current source 17.

The transfer unit 13 is controlled by a signal Vtx, and transfers the charge that has been photoelectrically converted by the photoelectric conversion unit 12 to the floating diffusion 15. In other words, the transfer unit 13 constitutes a charge transfer path between the photoelectric conversion unit 12 and the floating diffusion 15. The floating diffusion 15 holds (i.e. accumulates) charge. The amplification unit 16 amplifies a signal based upon the charge held by the floating diffusion 15, and outputs the result to a signal line 18. In the example shown in FIG. 3, the amplification unit 16 is constituted by a transistor M3 whose drain terminal, gate terminal, and source terminal are respectively connected to a power supply VDD, to the floating diffusion 15, and to the current source 17. The amplification unit 16 functions as a part of a source follower circuit that uses the current source 17 as a load current source.

The discharge unit 14 (which is a resetting unit) is controlled by a signal Vrst, and discharges the charge of the floating diffusion 15 and resets the potential of the floating diffusion 15 to a reset potential (which is a reference potential). The transfer unit 13 and the discharge unit 14 may, for example, be respectively constituted by a transistor M1 and by a transistor M2. The readout section 20 reads out a signal corresponding to the charge transferred from the photoelectric conversion unit 12 to the floating diffusion 15 by the transfer unit 13, to the signal line 18. The signal (a pixel signal) read out to the signal line 18 is inputted to an A/D conversion unit 200 (refer to FIG. 4) either directly or after amplification by an amplification circuit or the like.

FIG. 4 is a circuit diagram showing the structure of an A/D conversion unit and a signal generation unit according to the first embodiment. The image sensor 3 includes the analog/digital conversion unit (A/D conversion unit) 200 that is of the successive approximation type and that converts the analog signal outputted from the pixel 10 to a digital signal having a predetermined number of bits, and a signal generation unit 210. The A/D conversion unit 200 includes a comparison unit 40, a storage unit 50, and a capacitor unit 100, and, for example, one such A/D conversion unit may be provided for each of the pixels 10. It should be understood that a control unit 60 could also be included in the A/D conversion unit 200. The signal generation unit 210 is connected in common to the A/D conversion units 200 that are provided for each of the pixels 10. The signal generation unit 210 generates the reference signal Vref at a constant voltage, and supplies it to the A/D conversion units 200.

The capacitor unit 100 includes a first capacitor 71, a second capacitor 72, a third capacitor 73, a fourth capacitor 74, a fifth capacitor 75, a first switch SW81, a second switch SW82, a third switch SW83, and a fourth switch SW84. In the explanation of the A/D conversion unit 200 of this embodiment, for the sake of convenience, only the first capacitor 71 through the fifth capacitor 75 are shown. According to the A/D conversion resolution, the capacitor unit 100 is provided with a plurality of capacitors corresponding to the number of bits in the digital signal. In the example shown in FIG. 4, the A/D conversion unit 200 is an A/D converter whose resolving power is four bits, and it converts the signal from the pixel 10 into a four-bit digital signal.

The pixel 10 (not shown in the figure), the comparison unit 40, the first capacitor 71, the fifth capacitor 75, the first switch SW81, and the signal generation unit 210 are provided upon the first substrate 111. One such comparison unit 40 is provided for each of the pixels 10, and includes a comparator circuit and so on. The comparison unit 40 also includes a first input unit 41, a second input unit 42, and an output unit 43. The signal from the pixel 10 is inputted to the first input unit 41 as a signal Vin. And a signal Vcom generated by the capacitor unit 100 is inputted to the second input unit 42. The comparison unit 40 compares together the signal Vin and the signal Vcom, and outputs the result of this comparison to the output unit 43 as an output signal Vout. The signal Vout outputted from the output unit 43 is inputted to the control unit 60 via a signal line 130.

The second capacitor 72, the third capacitor 73, the second switch SW82, and the third switch SW83 are provided upon the second substrate 112. And the fourth capacitor 74 and the fourth switch SW84 are provided upon the third substrate 113. Each of the first capacitor 71 through the fifth capacitor 75 includes an element such as a MOS capacitor or a MIM (Metal-Insulator-Metal) capacitor or the like. And each of the first switch SW81 through the fourth switch SW84 includes an element such as a MOS transistor or the like.

The storage unit 50 and the control unit 60 are provided upon the fourth substrate 114. One of these storage units 50 is provided for each of the pixels 10, and includes a plurality of registers (which, for example, may be flip-flop circuits) corresponding to the bit numbers of the digital signal, and so on. On the basis of the results of comparison outputted by the comparison unit 40, the control unit 60 stores in the storage unit 50 a digital signal corresponding to the analog signal outputted from the pixel 10.

The capacitor unit 100 generates the signal Vcom on the basis of the signal Vref inputted from the signal generation unit 210 via the signal line 131, and outputs it to the comparison unit 40. The signal Vcom is a reference signal (i.e. a comparison signal) that is used by the comparison unit 40 for comparison with the signal Vin. Each of the first capacitor 71 through the fourth capacitor 74 has a capacitance value in which binary weighting is performed in that order. For example, the first capacitor 71 through the fourth capacitor 74 may have respective capacitance values of 1C, 2C, 4C, and 8C. Moreover, the fifth capacitor 75 has a capacitance value of 1C.

One terminal (electrode) of each of the first capacitor 71 through the fourth capacitor 74 is connected to the second input unit 42 of the comparison unit 40, while the other terminals (electrodes) of the first capacitor 71 through the fourth capacitor 74 are respectively connected to the switches SW81 through SW84. Each of the switches SW81 through SW84 can selectively connect the first capacitor 71 through the fourth capacitor 74 either to a GND line or to the signal line 131. Thus, each of the other terminals of the first capacitor 71 through the fourth capacitor 74 is connected either to the GND line or to the signal line 131.

The control unit 60 outputs control signals via the storage unit 50 to the switches SW81 through SW84, and changes over the destinations to which the first capacitor 71 through the fourth capacitor 74 are electrically connected by changing over the connection states of the switches SW81 through SW84. The control unit 60 changes over the signal level of the signal Vcom inputted to the comparison unit 40 by controlling the capacitance values of the capacitors that are connected between the comparison unit 40 and the signal generation unit 210. The A/D conversion unit 200 performs binary searching a plurality of times by sequentially changing the signal Vcom, and thereby generates a digital signal that corresponds to the signal outputted from the pixel 10. It should be understood that an example of the operation of the A/D conversion unit 200 will be described hereinafter in detail with reference to FIG. 5.

In this embodiment, the first capacitor 71 through the fourth capacitor 74 that are used in the A/D conversion unit 200 are separated between and disposed upon the plurality of substrates. By doing this, it is possible to lay out the plurality of capacitors without increasing the chip area. And, as a result, it is possible to enhance the bit number (i.e. the resolution) of the A/D conversion process without increasing the chip area. Furthermore the first capacitor 71, which is the one among the first capacitor 71 through the fourth capacitor 74 that has the lowest capacitance value, is disposed more closely to the comparison unit 40 than the second capacitor 71, and so on. The first capacitor 71 is the capacitor for determining the lowest ranking bit of the digital signal. The fourth capacitor 74, which is the one among the first capacitor 71 through the fourth capacitor 74 that has the highest capacitance value, is disposed in the position furthest from the comparison unit 40. To put it in another manner, the capacitors having lower capacitance values are disposed in positions closer to the comparison unit 40 than the capacitors having large capacitance values. By providing the first capacitor 71 whose capacitance value is the minimum among the first capacitor 71 through the fourth capacitor 74 in the position that is closest to the comparison unit 40, it becomes possible to reduce the influence of parasitic capacitance upon the first capacitor 71. Due to this, it is possible to implement high accuracy A/D conversion.

FIG. 5 is a figure for explanation of an example of operation of the A/D conversion unit according to the first embodiment. In FIG. 5, the voltage level of the signal is shown upon the vertical axis, and time is shown upon the horizontal axis. FIG. 5 shows an example in which four bit A/D conversion is performed, from a first bit (the MSB) to a fourth bit (the LSB).

After the signal that has been outputted from the pixel 10 is inputted to the first input unit 41 of the comparison unit 40, during the interval until the time point t1, the control unit 60 sets the control signal inputted to the switch SW84 to high level and sets the control signals inputted to each of the switches SW81 through SW83 to low level. Due to high level being inputted to the switch SW84, the fourth capacitor 74 is connected to the signal line 131. Due to low level being inputted to each of the switches SW81 through SW83, each of the first capacitor 71 through the third capacitor 73 is connected to the GND line. As a result, the voltage of the signal Vcom becomes ½ Vref, which is obtained as the voltage of the signal Vref multiplied by the ratio of the capacitance value of the fourth capacitor 74 to the sum of the capacitance values of the first capacitor 71 through the fifth capacitor 75. In the example shown in FIG. 5, since the voltage of the signal Vin is smaller than ½ Vref, accordingly the comparison unit 40 outputs an output signal Vout at low level to the control unit 60 as the result of comparison. Therefore, on the basis of the comparison result by the comparison unit 40, the control unit 60 stores “0” in the storage unit 50 as the first bit (i.e. the MSB).

At the time point t2, on the basis of the comparison result, the control unit 60 sets the control signal inputted to the switch SW84 to low level. Moreover, the control unit 60 sets the control signal inputted to the switch SW83 to high level, and sets both of the control signals inputted to the switch SW81 and to the switch SW82 to low level. Thus, the fourth capacitor 74 is connected to the GND line, the third capacitor 73 is connected to the signal line 131, and the first capacitor 71 and the second capacitor 72 are both connected to the GND line. Due to this, the voltage of the signal Vcom becomes ¼ Vref. Since the voltage of the signal Vin is higher than ¼ Vref, accordingly the comparison unit 40 outputs an output signal Vout at high level to the control unit 60 as the result of comparison. On the basis of the comparison result by the comparison unit 40, the control unit 60 stores “1” in the storage unit 50 as the second bit.

At the time point t3, on the basis of the comparison result, the control unit 60 sets the control signal inputted to the switch SW84 to low level, and sets the control signal inputted to the switch SW83 to high level. Moreover, the control unit 60 sets the control signal inputted to the switch SW82 to high level, and sets the control signal inputted to the switch SW81 to low level. Thus, the fourth capacitor 74 is connected to the GND line, the third capacitor 73 and the second capacitor 72 are connected to the signal line 131, and the first capacitor 71 is connected to the GND line. Due to this, the voltage of the signal Vcom becomes (¼+⅛) Vref. Since the voltage of the signal Vin is lower than (¼+⅛) Vref, accordingly the comparison unit 40 outputs an output signal Vout at low level to the control unit 60 as the result of comparison. On the basis of the comparison result by the comparison unit 40, the control unit 60 stores “0” in the storage unit 50 as the third bit.

At the time point t4, on the basis of the comparison result, the control unit 60 sets the control signal inputted to the switch SW84 to low level, sets the control signal inputted to the switch SW83 to high level, and sets the control signal inputted to the switch SW82 to low level. Moreover, the control unit 60 sets the control signal inputted to the switch SW81 to high level. Thus, the fourth capacitor 74 is connected to the GND line, the third capacitor 73 is connected to the signal line 131, the second capacitor 72 is connected to the GND line, and the first capacitor 71 is connected to the signal line 131. Due to this, the voltage of the signal Vcom becomes (¼+ 1/16) Vref. Since the voltage of the signal Vin is lower than (¼+ 1/16) Vref, accordingly the comparison unit 40 outputs an output signal Vout at low level to the control unit 60 as the result of comparison. On the basis of the comparison result by the comparison unit 40, the control unit 60 stores “0” in the storage unit 50 as the fourth bit (i.e. the LSB).

By the above described successive approximation processing, the A/D conversion unit 200 converts the value of the signal outputted from the pixel 10 into the digital signal “0100”. The resulting digital signal that is stored in the storage unit 50 of the A/D conversion unit 200 is outputted to a signal processing unit 170 of a subsequent stage (not shown in the figures). Signal processing such as processing to correct the value of the signal to match the A/D conversion gain and so on is performed by that signal processing unit 170 upon the signal outputted from the A/D conversion unit 200, and the result is outputted as an image signal to the control unit 4 of the image capturing device 1.

A signal line 132 to which the first capacitor 71 through the fourth capacitor 74 are connected is a signal line that passes through the first substrate 111, the second substrate 112, and the third substrate 113, and is a signal line that employs the through electrodes 110 or the connection portions 109 such as bumps or the like shown in FIG. 2. Due to this, parasitic capacitance is added on the signal line 132 due to the parasitic capacitance of the wiring, the junction capacitances between the layers, and so on. The first capacitor 71 which is used for determination of the lowest ranking bit has the smallest capacitance value as compared with the second capacitor 72 through the fourth capacitor 74, and accordingly experiences the great influence due to the parasitic capacitance. Therefore, in this embodiment, the first capacitor 71 is disposed upon the first substrate 111, which is the same as the substrate for the comparison unit 40. Moreover it is considered that the fourth capacitor 74, which has the highest capacitance value among the first capacitor 71 through the fourth capacitor 74, will experience a comparatively small influence due to the parasitic capacitance. Therefore, the fourth capacitor 74 is disposed upon the third substrate 113, which is the one that is distant from the comparison unit 40 which is upon the first substrate 111. Due to this, it is possible to reduce the deviations of the capacitance values due to the parasitic capacitance, and thus it is possible to reduce the conversion error due to A/D conversion. When the first capacitor 71 through the fourth capacitor 74 are disposed separately upon a plurality of substrates in this manner, it is possible to reduce the deviations of the capacitance values due to influence of the parasitic capacitance, and thereby to enhance the accuracy of the A/D conversion.

According to the embodiment described above, the following beneficial operational effects are obtained.

(1) The image sensor 3 includes the photoelectric conversion unit 12 that photoelectrically converts incident light and generates a charge, the comparison unit 40 having the input unit 42 into which is inputted a reference signal (the signal Vcom) for comparison with a signal corresponding to the charge generated by the photoelectric conversion unit 12, a first circuit layer (i.e. the first substrate 111) having a first capacitor (for example, the first capacitor 71) that is connected to the input unit 42, and a second circuit layer (i.e. the second substrate 112) that is laminated to the first circuit layer and has a second capacitor (for example, the second capacitor 72) that is connected to the input unit 42. In this embodiment, the first capacitor 71 through the fourth capacitor 74 are disposed separately upon a plurality of substrates. Due to this, it is possible to arrange the plurality of capacitors for processing the signal from the pixel 10 without increasing the chip area. Furthermore, by disposing the first capacitor 71 through the fourth capacitor 74 separately upon the plurality of substrates, it is possible to prevent the opening ratio of the pixels 10 from decreasing.

(2) The image sensor 3 includes the photoelectric conversion unit 12 that photoelectrically converts incident light and generates a charge, the comparison unit 40 that outputs a signal on the basis of comparison between a signal corresponding to the charge generated by the photoelectric conversion unit 12 and a reference signal (i.e. the signal Vcom), the first circuit layer (i.e. the first substrate 111) having a first capacitor (for example, the first capacitor 71) that is connected to the comparison unit 40, and the second circuit layer (i.e. the second substrate 112) that is laminated to the first circuit layer and that has a second capacitor (for example, the second capacitor 72) that is connected to the comparison unit 40. Due to this, it is possible to dispose the plurality of capacitors for processing the signal from the pixel 10 without increasing the chip area. Furthermore, it is possible to prevent the opening ratio of the pixels 10 from being reduced.

(3) The storage unit 50 is provided which stores the digital signal based upon the signal outputted from the comparison unit 40. The comparison unit 40, the first capacitor, the second capacitor, and the storage unit 50 together constitute the A/D conversion unit that converts the signal corresponding to the charge generated by the photoelectric conversion unit 12 into a digital signal. Since this is done, accordingly it is possible to dispose the plurality of capacitors without increasing the chip area, and also it is possible to enhance the resolution of the A/D conversion.

(4) The first capacitor is a capacitor whose capacitance value is smaller than that of the second capacitor. In this embodiment, the first capacitor 71 whose capacitance value is the smallest among the first capacitor 71 through the fourth capacitor 74 is the one that is disposed in the position close to the comparison unit 40. Due to this, it is possible to reduce its deviation from its capacitance value due to the influence of parasitic capacitance, and therefore it is possible to prevent deterioration of the accuracy of the A/D conversion caused by differential non-linearity (DNL). As a result, it is possible to implement highly accurate A/D conversion.

Second Embodiment

An image sensor 3 according to a second embodiment will now be explained with reference to FIG. 6. It should be understood that, in the figure, the same reference symbols are appended to elements that are the same as or that correspond to elements in the first embodiment, and the explanation will principally concentrate upon the features of difference from the image sensor 3 of the first embodiment. FIG. 6 is a circuit diagram showing the structure of an A/D conversion unit and a signal generation unit according to the second embodiment. The image sensor 3 according to the second embodiment includes a first capacitance adjustment unit 220, a second capacitance adjustment unit 230, and a third capacitance adjustment unit 240.

The first capacitance adjustment unit 220 through a third capacitance adjustment unit 240 are circuits that correct for the influence of parasitic capacitances, added to the second capacitor 72 through the fourth capacitor 74 respectively. The first capacitance adjustment unit 220 includes a capacitor 211, a capacitor 212, a switch SW213, and a switch 214. The capacitor 212 of the first capacitance adjustment unit 220 is connected in parallel with the second capacitor 72. The capacitor 211 is connected in series with the capacitor 212. The switch SW214 is controlled by a control signal outputted from the control unit 60, and changes over the point to which the capacitor 212 is electrically connected. Furthermore, the switch SW213 is controlled by another control signal outputted from the control unit 60, and changes over the state of electrical connection between the second capacitor 72 and the capacitor 211.

By a control signal being supplied from the control unit 60 to turn the switch 213 and the switch 214 ON, a capacitance obtained by combining the capacitor 211 and the capacitor 212 connected in series is added to the capacitance of the second capacitor 72. When the first capacitor 71 through the fourth capacitor 74 are disposed separately upon the plurality of substrates, variations occur in the values of capacitance between the substrates. Accordingly it is possible to reduce the variation of the capacitance values due to the influence of the parasitic capacitance by controlling the states of continuity of the switch 213 and the switch 214 according to the parasitic capacitance formed on the signal line 132, and by thereby adjusting the capacitance added to the second capacitor 72. Moreover, it is possible to reduce the values of the capacitances between the substrates.

Furthermore since, in this embodiment, the capacitor 212 is connected to the second capacitor 72 via the capacitor 211, accordingly it is possible to perform fine adjustment of the value of the capacitance added to the second capacitor 72. Since the second capacitance adjustment unit 230 and the third capacitance adjustment unit 240 have similar structures and functions to those of the first capacitance adjustment unit 220, accordingly explanation thereof will be mitted. It should be understood that the numbers of capacitors and switches included in each of the first capacitance adjustment unit 220 through the third capacitance adjustment unit 240 may be determined as desired. Moreover, it would also be acceptable to arrange not to provide the capacitor 211 and the switch 213. In this case it would be possible, by turning the switch 214 ON, to connect the capacitor 212 directly to the second capacitor 72, and it would be possible to add a larger capacitance as compared with the case of connection via the capacitor 211.

According to the embodiment described above, in addition to the same beneficial effects as in the case of the first embodiment, the following beneficial operational effects are obtained.

(5) The second circuit layer (i.e. the second substrate 112) has the capacitance adjustment unit that includes a third capacitor (i.e. the capacitor 212) that is connected in parallel with the second capacitor. In this embodiment, the first capacitance adjustment unit 220 through the third capacitance adjustment unit 240 are disposed corresponding to the second capacitor 72 through the fourth capacitor 74. Due to this, it is possible to adjust the values of the capacitances that are added to the second capacitor 72 through the fourth capacitor 74, so that it is possible to reduce variations in their capacitance values due to the influence of parasitic capacitances. Moreover, it is also possible to reduce variations in the capacitance values between the substrates. As a result, it is possible to implement highly accurate A/D conversion.

(6) The capacitance adjustment unit also has a fourth capacitor (i.e. the capacitor 211) that is connected in series with the third capacitor (i.e. the capacitor 212). In this embodiment, the capacitance obtained by combining the capacitor 211 and the capacitor 212 connected in series is added to the second capacitor 72. Due to this, it is possible to add a smaller capacitance, as compared with the case when the capacitance value of the capacitor 212 is added to the second capacitor 72.

Third Embodiment

An image sensor 3 according to a third embodiment will now be explained with reference to FIG. 7. It should be understood that, in this figure, the same reference symbols are appended to elements that are the same as or that correspond to elements in the first embodiment, and the explanation will principally concentrate upon the features of difference from the image sensor 3 of the first embodiment. FIG. 7 is a circuit diagram showing the structure of a PGA unit according to the third embodiment. The image sensor 3 according to the third embodiment is built to include a programmable gain amp (PGA) unit 300 that amplifies the signal outputted from the pixel 10 by a predetermined gain (amplification factor). For example, a PGA unit 300 may be provided for each of the pixels 10, and each of them may be built to include an amplification unit (i.e. a comparison unit) 310, an input capacitor C1, a switch SW for resetting, switches SW1 through SW4 for gain setting, and feedback capacitors Cf1 through Cf4. It should be understood that the PGA unit 300 may include any desired number of feedback capacitors and switches for gain setting. In the PGA unit 300, the plurality of feedback capacitors and gain setting switches are provided to correspond to a plurality of gain setting values.

A pixel 10 (not shown in the figure), an amplification unit 310, an input capacitor C1, a switch SW for resetting, a switch SW1 for gain setting, and a feedback capacitor Cf1 are provided upon the first substrate 111. The signal Vin is inputted from the pixel 10 to one of the terminals of the input capacitor Ci. The amplification unit 310 outputs from its output terminal 313 a signal produced by amplifying the difference between a signal inputted to its non-inverting input terminal 311 and a signal inputted to its inverting input terminal 312. A reference signal Vref having a fixed voltage is inputted to the non-inverting input terminal 311 of the amplification unit 310. The switch SW for resetting is controlled to be set to ON and OFF by a control signal rst. When the reset switch SW is set to ON, the inverting input terminal 312 of the amplification unit 310 and its output terminal 313 are electrically connected, and the voltage of the signal inputted to the inverting input terminal 312 is reset to the voltage of the reference signal Vref.

Switches SW2 through SW4 for gain setting and feedback capacitors Cf2 through Cf4 are provided upon the second substrate 112. For example, the feedback capacitors Cf1 through Cf4 may have capacitance values of 1C, 4C, 8C, and 16C respectively. Moreover, the input capacitor Ci may, for example, have a capacitance value of 16C.

The gain setting switches SW1 through SW4 are respectively controlled to be set to ON and OFF by control signals sw1 through sw4. It is possible for the capacitance electrically connected between the inverting input terminal 312 of the amplification unit 310 and its output terminal 313 to be changed by the gain setting switches SW1 through SW4 being controlled to be set to ON and OFF, and thereby it is possible to change the gain of the PGA unit 300. The gain of the PGA unit 300 becomes the ratio (−Ci/Cf) between the value Ci of the capacitance of the input capacitor Ci and the value Cf of the capacitance due to those of the feedback capacitors Cf1 through Cf4 that are selected by the control signals sw1 through sw4. Moreover, the output signal Vout of the PGA unit 300 may, for example, be given by the following Equation (1):

Vout=(−Ci/Cf)×ΔVin+Vref  (1)

The signal Vout outputted from the PGA unit 300 may, for example, be inputted to an A/D conversion unit 200 (not shown in the figures).

In this embodiment, the feedback capacitors Cf1 through Cf4 used in the PGA unit 300 are disposed upon the plurality of substrates. Due to this, it is possible to dispose the plurality of capacitors without increasing the chip area. As a result, it is possible to increase the range over which the gain of the PGA unit 300 can be varied. Furthermore, in order to increase the gain of the PGA unit 300, there is the method of increasing the capacitance value Ci or the method of reducing the capacitance value Cf, but the method of reducing the capacitance value Cf is generally employed, in order to avoid increase of the chip area. However, when the capacitance value Cf is reduced, the error from the specified gain becomes larger, since the influence experienced due to the parasitic capacitances becomes greater. Accordingly the feedback capacitor Cf1, which is the one among the feedback capacitors Cf1 through Cf4 that has the minimum capacitance value, is disposed in a position close to the amplification unit 310. Due to this, it is possible to reduce the influence of the parasitic capacitance upon the feedback capacitor Cf1. And, by doing this, it is possible to reduce the error in the gain of the PGA unit 300, and therefore to implement signal amplification at high accuracy.

According to the embodiment described above, the following beneficial operational effect is obtained.

(1) The amplification unit (i.e. the PGA unit 300) that amplifies the signal generated corresponding to the charge generated by the photoelectric conversion unit 12 includes the comparison unit (i.e. the amplification unit 310), the first capacitor (for example, the feedback capacitor Cf1), and the second capacitor (for example, the feedback capacitor Cf2), and is further provided with the fifth capacitor (i.e. the input capacitor Ci) to which the signal corresponding to the charge generated by the photoelectric conversion unit 12 is inputted, and that is connected in series with the first capacitor and the second capacitor. Since the structure is adopted, accordingly it is possible to dispose the plurality of capacitors without increasing the chip area, and it is possible to increase the range over which the gain can be varied. Furthermore, in this embodiment, the feedback capacitor Cf1, which is the one among the feedback capacitors Cf1 through Cf4 that has the minimum capacitance value, is disposed in a position close to the amplification unit 310. Due to this, it is possible to reduce the influence of the parasitic capacitance upon the feedback capacitor Cf1, and it is possible to reduce the error in the gain of the PGA unit 300.

The following modifications are also within the range of these embodiments; and it would also be possible to combine one or a plurality of the following variant embodiments with one or more of the embodiments described above.

First Variant Embodiment

FIG. 8 is a circuit diagram showing the structures of an A/D conversion unit and of a signal generation unit according to a first variant embodiment. In the example shown in FIG. 8, the capacitor unit 100 of the A/D conversion unit 200, as compared with the first embodiment, further includes a sixth capacitor 76 through a ninth capacitor 79 and a sixth switch SW86 through a ninth switch SW89. Moreover, the capacitor unit 100 includes a splitting capacitor 80 that is provided between the capacitors for the lower ranking bits (i.e. the sixth capacitor 76 through the ninth capacitor 79) and the capacitors for the higher ranking bits (i.e. the first capacitor 71 through the fourth capacitor 74). In the example shown in FIG. 8, the capacitance value of the split capacitor 80 is (16/15)C. The A/D conversion unit 200 is an A/D converter whose resolution is 8 bits.

Due to the provision of the split capacitor 80 to the capacitor unit 100, it is possible to reduce the sum total of the capacitance values, as compared to the case in which the capacitance values of the first capacitor 71 through the fourth capacitor 74 and the sixth capacitor 76 through the ninth capacitor 79 are given values that are determined in binary weight. For example, it is possible to reduce the capacitance values of each of the sixth capacitor 76 through the ninth capacitor 79. As a result, it is possible to reduce the circuit area of the image sensor 3. An A/D conversion unit 200 of the type shown in FIG. 8 is called a “Two-Step-C-Array” type A/D conversion unit or the like. Moreover, a capacitor unit 100 of the type shown in FIG. 8 is called a “split-capacitor-DAC” or the like.

In the variant embodiment the sixth capacitor 76, which is the one among the capacitors for the lower ranking bits (i.e. the sixth capacitor 76 through the ninth capacitor 79) which has the minimum capacitance value, is disposed upon the first substrate 111, just as is the comparison unit 40. Moreover the first capacitor 71, which is the one among the capacitors for the higher ranking bits (i.e. the first capacitor 71 through the fourth capacitor 74) which has the minimum capacitance value, is likewise disposed upon the first substrate 111, just as is the comparison unit 40. And furthermore the split capacitor 80 is similarly disposed upon the first substrate 111, just as is the comparison unit 40. Due to this, it is possible to reduce the influence of deviation of the capacitance values due to the parasitic capacitances, and thus it is possible to reduce the conversion error of the A/D conversion process.

Second Variant Embodiment

In the embodiments and the variant embodiment described above, examples have been explained in which the present invention has been applied to an A/D conversion unit of the successive approximation type or to an A/D conversion unit of the Two-Step-C-Array type. However, it would also be possible to apply the present invention to a cyclic type A/D conversion unit.

Third Variant Embodiment

In the first embodiment described above, an example was explained in which four substrates were laminated together, with the first substrate 111 bearing the pixel 10, the comparison unit 40, the first capacitor 71, and the fifth capacitor 75, the second substrate 112 bearing the second capacitor 72 and the third capacitor 73, the third substrate 113 bearing the fourth capacitor 74, and the fourth substrate 114 bearing the control unit 60 and the storage unit 50. However, the number of substrates should not be considered as being limited to four. For example, it would also be acceptable for the image sensor 3 to include five substrates laminated together, with the first substrate 111 bearing the pixel 10, the comparison unit 40, the first capacitor 71, and the fifth capacitor 75, the second substrate 112 bearing the second capacitor 72, the third substrate 113 bearing the third capacitor 73, the fourth substrate 114 bearing the fourth capacitor 74, and a fifth substrate 115 bearing the control unit 60 and the storage unit 50. Moreover, it would also be acceptable for the image sensor 3 to include six substrates laminated together, with the first substrate 111 bearing the pixel 10, the comparison unit 40, and the first capacitor 71, the second substrate 112 bearing the fifth capacitor 75, the third substrate 113 bearing the second capacitor 72, the fourth substrate 114 bearing the third capacitor 73, the fifth substrate 115 bearing the fourth capacitor 74, and a sixth substrate 115 bearing the control unit 60 and the storage unit 50. It would also be possible for the pixel 10 and the comparison unit 40 to be provided upon different substrates. Moreover, it would also be acceptable for the comparison unit 40 and the first capacitor 71 to be provided upon different substrates. For example, it will be acceptable for the comparison unit 40 to be provided upon the first substrate 111, for the first capacitor 71 to be provided upon the second substrate 112, and for the second capacitor 72 through the fourth capacitor 74 to be provided upon the third substrate 113. Moreover, it would also be possible for the first capacitor 71 and the second capacitor 72 to be provided upon the same substrate. In this case, the first capacitor 71 should be provided in a position that is closer to the comparison unit 40 than the second capacitor 72. It would also be acceptable for the photoelectric conversion unit 12, the comparison unit 40, and the first capacitor 71 to be provided upon the same substrate (for example, upon the first substrate 111). Yet further, it would also be acceptable for the photoelectric conversion unit 12, the comparison unit 40, the first capacitor 71, and the second capacitor 72 to be provided upon the same substrate.

Fourth Variant Embodiment

Each of the first capacitor 71 through the ninth capacitor 79 has been explained as being a single capacitor. However, it would also be possible for each of the first capacitor 71 through the ninth capacitor 79 to be built up from a plurality of capacitors. In this case, the combined capacity of the corresponding plurality of capacitors will become the capacitance of each of the first capacitor 71 through the ninth capacitor 79. Furthermore, it would also be acceptable for each of the first capacitor 71 through the ninth capacitor 79 to be built up from a plurality of capacitors having the same capacitance value. For example, the first capacitor 71 may be made up from two capacitors connected in parallel, each having a capacitance value of ½ C. The combined capacitance of the two capacitors that are connected in parallel is therefore C, and this combined capacitance C of the two capacitors becomes the capacitance of the first capacitor 71. In a similar manner, the second capacitor 72 may be made up from four capacitors connected in parallel, each having a capacitance value of ½ C. The combined capacitance of the four capacitors that are connected in parallel is therefore 2C, and this combined capacitance 2C of the four capacitors becomes the capacitance of the second capacitor 72. Similar structures can be adopted for the third capacitor 73 through the ninth capacitor 79 as well.

It should be understood that the capacitance values of the capacitors, the number thereof, and their connections are not to be considered as being limited by the above description. For example, it would also be acceptable to arrange for the first capacitor 71 to have a capacitance value of 3C, and for it to be made up from three capacitors connected in series. And it would also be acceptable to arrange for the second capacitor 72 to have a capacitance value of 4C, and for it to be made up from two capacitors connected in series.

Fifth Variant Embodiment

In the embodiments described above, examples have been explained in which the image sensor 3 was built as a backside-illuminated type element. However, it would also be acceptable for the image sensor 3 to be built as a front-illuminated type having its wiring layer on its side upon which light is incident.

Sixth Variant Embodiment

In the embodiments described above, examples in which photodiodes were used as the photoelectric conversion units 12 have been explained. However, it would also be acceptable to arrange to employ a photoelectric conversion film as the photoelectric conversion unit 12.

Seventh Variant Embodiment

Any of the image sensor 3 explained in the embodiments described above may also be applied to a camera, a smartphone, a tablet, a camera included in a PC, an onboard camera, or the like.

The content of the disclosure of the following application, upon which priority is claimed, is hereby incorporated herein by reference: Japanese Patent Application 101,276 of 2016 (filed on 20 May 2016).

REFERENCE SIGNS LIST

-   3: image sensor -   12: photoelectric conversion unit -   10: pixel -   40: comparison unit -   200: A/D conversion unit 

1. An image sensor, comprising: a photoelectric conversion unit that photoelectrically converts incident light and generates a charge; and an A/D conversion unit that converts an analog signal generated due to the charge generated by the photoelectric conversion unit into a digital signal, wherein: the A/D conversion unit includes a comparison unit that compares the analog signal with a reference signal, a first circuit layer including a first capacitor for generating the reference signal, and a second circuit layer laminated to the first circuit layer and including a second capacitor for generating the reference signal. 